This invention relates to a method of manufacturing a semiconductor random access memory cell (DRAM cell), particularly, which has a large stacked storage capacity.
A DRAM cell includes a transistor of which a drain-source is connected between a bit line and cell node, and a storage capacitor connected between the cell node and a cell plate. The increment of memory capacity is in need of nearly constant and large storage capacity of the cell, and also reduction in size. In order to increase the cell storage capacity, capacitor cells formed with a three dimensional structure, such as a trench capacitor cell and a stacked capacitor cell, have been researched.
Whereas the trench capacitor cell has an advantage of large storage capacity, it is not necessarily easy to manufacture because of the problems like a punch-through and a leakage current between trenches. On the contrary, manufacturing the staked capacitor cell is easy to carry out, while it has been considered about the limitation of sufficiently large storage capacity. A method for increasing capacity of the stacked capacitor cell is connecting two capacitor cells in parallel between a cell node and a cell plate. Such prior art is disposed in the U.S. Pat. No. 4,735,915. In this prior art, however, it is difficult to achieve sufficient storage capacity because it can't provide a large surface area for the storage capacitor.
The other method for increasing capacity of the stacked capacitor is extending the area of storage capacity by forming multiple insulating layers between the cell node and the cell plate. Such a prior art is disclosed in "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS" IEDM, issued in 1988, PP.592-595. This structure, however, has a difficulty in manufacturing.